David's Online CRC Unroller

This web page computes the equations for the next state of a CRC circuit that takes in multiple bits of data per clock and it generates the verilog code for the equations. You provide the CRC length, the polynomial and the number of databits. It defaults to the 32 bit CCITT CRC over 32 bits of data.

Generator Polynomial (in Hex):
CRC Size (in bits):
Input databits (in bits):


// Equations for 7 bit CRC taking in 32 databits per clock.
// See Polynomial_representations_of_cyclic_redundancy_checks for standard CRC polynomials.
// Generator Polynomial 0x9: X^7 + X^3 + 1
// x[6:0] are the state bits. d[31:0] are the input data bits
x[0] <= x[5] ^ x[6] ^ d[6] ^ d[13] ^ d[20] ^ d[27];
x[1] <= x[0] ^ x[6] ^ d[5] ^ d[12] ^ d[19] ^ d[26];
x[2] <= x[0] ^ x[1] ^ d[4] ^ d[11] ^ d[18] ^ d[25];
x[3] <= x[1] ^ x[2] ^ x[5] ^ x[6] ^ d[3] ^ d[10] ^ d[17] ^ d[24] ^ d[31];
x[4] <= x[2] ^ x[3] ^ x[6] ^ d[2] ^ d[9] ^ d[16] ^ d[23] ^ d[30];
x[5] <= x[3] ^ x[4] ^ d[1] ^ d[8] ^ d[15] ^ d[22] ^ d[29];
x[6] <= x[4] ^ x[5] ^ d[0] ^ d[7] ^ d[14] ^ d[21] ^ d[28];

Here are some common CRCs listed on Wikipedia, to try

CRC-3 (GSM)

CRC-4-ITU

CRC-5-EPC

CRC-5-USB

CRC-6-CDMA2000-A

CRC-6-CDMA2000-B

CRC-6-DARC

CRC-6-GSM

CRC-6-ITU

CRC-7

CRC-7-MVB

CRC-8 DVB S2

CRC-16 CCITT


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